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Memory Maps
5.3
5.3.1
Memory-mapped components
Interrupt controller
The CF1_INTC register map is sparsely populated, but retains compatibility with earlier ColdFire
interrupt-controller definitions. The CF1_INTC occupies the upper 64 bytes of the 4-GB address space
and all memory locations are accessed as 8-bit (byte) operands. This 64-byte space includes the
program-visible interrupt controller registers as well as the space used for interrupt-acknowledge (IACK)
cycles.
Table 5-15 is a summary of CF1_INTC user-accessible peripheral registers and control bits. Cells that are
not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit is always read
as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could be read as 1s or 0s.
When writing to these bits, write a 0 unless otherwise specified.
5.3.2
Nonvolatile register area
There is a nonvolatile register area consisting of a block of 4 bytes in flash memory at
0x(00)00_3FFB–0x(00)00_3FFF. The byte at 0x(00)00_3FFF is allocated to flash protection and security
functions. Additionally, the byte at 0x(00)00_3FFE is used to initialize boot options for the device. See
Because the nonvolatile register locations are flash memory, they must be erased and programmed like
other flash memory locations.
5.3.3
RGPIO
The section of memory at 0x(00)C0_0000 is assigned for use by the ColdFire Rapid GPIO module. See
module.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
49
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